A Fast Integrating Eight - Bit Bilinear Adc ’

A fast gated charge integrating ADC has been developed for measuring short photomultiplier pulses at very high event rates. The circuit is bilinear with 100 pC full scale and a least count of 150 fC. It features dc coupling, a miniium gate width of 20 ns, a minimum time between events of 200 ns plus gate width, a two event buffer, and front-end zero suppression with 100 ns read time per hit channel. Five hundred channels have been built and installed in the rare Ki decay experiment E791 at Brookhaven National Laboratory. INTRODUCTION As high energy physics experiments move towards higher event rates, it is necessary to develop electronics capable of digitizing, storing and reading out signals from a detector with little or no dead time. Experiment E791 at Brookhaven National Laboratory is an experiment to search for rare Ki-+ pe with a branching ratio of lo-12. In this experiment individual detector channels can experience rates on the order of a megahertz and the rate of low level triggers can exceed tens of kilohertz. Figure 1 shows the readout architecture of E791 and is discussed in detail elsewhere [l]. Of interest in this report is the completely 'Flash " front-end electronics and parallel pipelined readout architecture with sparse data scan, In less than 200 ns all times and charges are digitized and latched. There are two levels of event buffer including " Hit " information following digitization, thus allowing sparse readout of one event at up to 509 Mbytes per second while another event is being digitized. Events may also be discarded at either buffer stage via a level-two trigger decision by resetting a bit within the readout supervisor. We have developed a unique charge-integrating bilinear fast ADC as part of this system. The primary function of the ADC is to digitize photomultiplier signals from a large lead-glass array, but signals from a Cerenkov counter and assorted scintillation counters (about 500 channels in all) are also digitized. In this report, we describe the design and performance of this ADC. CIRCUIT DESIGN Several factors constrain the design of the ADC and ass-ciated readout electronics. (1) Physics considerations dictated a dynamic range of approximately nine bits with 100 pC full scale. (2) Since event rates are both hinh and random. dc cou~linn (31 (4) (5) was necessary to prevent Up&e pile up. " ' Some channels would eventually be used in the …